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| 3d glasses 8-bit flash type mcu HT45FH3T revision: v1.10 date: ? a ? 1 ?? ? 01 ? ? a ? 1 ?? ? 01 ?
rev. 1.10 ? ? a ? 1 ?? ? 01 ? rev. 1.10 ? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu table of contents eates cpu features ......................................................................................................................... 6 peripheral features ................................................................................................................. 6 general description ........................................................................................ ? block diagram .................................................................................................. ? pin assignment ........... ..................................................................................... 8 pin description .......... ...................................................................................... 8 internal connection description .......... ........................................................ 10 absolute ?aximum ratings .......................................................................... 10 d.c. characteristics ........................................................................................ 11 a.c. characteristics ....................................................................................... 1? a/d converter electrical characteristics ........... .......................................... 1? lvd & lvr electrical characteristics .......................................................... 1? ldo regulator characteristics .................................................................... 1? level converter characteristics ................................................................... 14 over v oltage circuit characteristics ............................................................ 14 power on reset characteristics ................................................................... 14 oscillator temperature/frequenc? characteristics ................................... 15 s?stem architecture ...................................................................................... 16 clocking and pipelining ......................................................................................................... 16 program counter ................................................................................................................... 1 ? stack ..................................................................................................................................... 18 arithmetic and logic unit C alu ........................................................................................... 18 flash program ?emor? ................................................................................. 19 structure ................................................................................................................................ 19 special vectors ..................................................................................................................... 19 look-up table ............. ........................................................................................................... ? 0 table program example ........................................................................................................ ? 1 in circuit programming ......................................................................................................... ?? on-chip debug support C ocds ......................................................................................... ?? ra? data ?emor? ......................................................................................... ?? structure ................................................................................................................................ ?? special function register description ........................................................ ?5 indirect addressing registers C iar0 ? iar1 ......................................................................... ? 5 ? emor ? pointers C ? p0 ? ? p1 .............................................................................................. ? 5 accumulator C acc ............................................................................................................... ? 6 program counter low register C pcl .................................................................................. ? 6 look-up table registers C tblp ? tbhp ? tblh ..................................................................... ? 6 rev. 1.10 ? ?a? 1?? ?01? rev. 1.10 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu status register C status .................................................................................................... ? 6 oscillator ........................................................................................................ 28 oscillator overview ............. .................................................................................................. ? 8 system clock confgurations ................................................................................................ ? 8 internal rc oscillator C hirc ............. .................................................................................. ? 9 internal ?? khz oscillator C lirc ........................................................................................... ? 9 operating modes and system clocks ......................................................... 29 s ? stem clocks ...................................................................................................................... ? 9 s ? stem operation ? odes ...................................................................................................... ? 1 control register .................................................................................................................... ?? operating ? ode switching .................................................................................................... ? 4 nor ? al ? ode to slow ? ode switching ........................................................................... ? 5 slow ? ode to nor ? al ? ode switching .......................................................................... ? 5 entering the sleep0 ? ode .................................................................................................. ? 5 entering the sleep1 ? ode .................................................................................................. ? 5 entering the idle0 ? ode ...................................................................................................... ? 6 entering the idle1 ? ode ...................................................................................................... ? 6 standb ? current considerations ........................................................................................... ? 8 wake-up ................................................................................................................................ ? 8 watchdog timer ........... .................................................................................. 39 watchdog timer clock source .............................................................................................. ? 9 watchdog timer control register ............. ............................................................................ ? 9 watchdog timer operation ................................................................................................... 40 reset and initialisation .................................................................................. 41 reset functions ............. ....................................................................................................... 41 reset initial conditions ......................................................................................................... 44 input/output ports ......................................................................................... 47 pull-high resistors ................................................................................................................ 4 ? port a wake-up ............. ........................................................................................................ 48 i/o port control registers ..................................................................................................... 48 i/o pin structures .................................................................................................................. 49 programming considerations ............. ................................................................................... 50 timer modules C tm .......... ............................................................................ 50 introduction ........................................................................................................................... 50 t ? operation ............. ........................................................................................................... 51 t ? clock source ............. ...................................................................................................... 51 t ? interrupts ......................................................................................................................... 51 t ? external pins ................................................................................................................... 5 ? t ? input/output pin control register ................................................................................... 5 ? programming considerations ............. ................................................................................... 56 rev. 1.10 4 ? a ? 1 ?? ? 01 ? rev. 1.10 5 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu compact type tm C ctm (tm2, tm3) ........................................................... 57 compact t ? operation ......................................................................................................... 5 ? compact t ? pe t ? register description ................................................................................ 58 compact t ? pe t ? operation ? odes .................................................................................... 6 ? periodic type tm C ptm (tm0, tm1) ............................................................ 68 periodic t ? operation ............. ............................................................................................. 68 periodic t ? pe t ? register description ................................................................................. 69 periodic t ? pe t ? operation ? odes ...................................................................................... ? 6 analog to digital converter .......... ................................................................ 85 a/d overview ............. ........................................................................................................... 85 a/d converter register description ...................................................................................... 85 a/d converter data registers C adrl ? adrh ..................................................................... 86 a/d converter control registers C adcr0 ? adcr1 ? acerl ............................................... 86 a/d operation ....................................................................................................................... 89 a/d input pins ............. .......................................................................................................... 90 summar ? of a/d conversion steps ............. .......................................................................... 91 programming considerations ............. ................................................................................... 9 ? a/d transfer function ............. .............................................................................................. 9 ? a/d programming example ................................................................................................... 9 ? complementary pwm output ....................................................................... 95 over voltage protection ... ............................................................................ 96 ovp register ............. ........................................................................................................... 9 ? comparator cancellation function ....................................................................................... 100 interrupts ...................................................................................................... 101 interrupt registers ............................................................................................................... 101 interrupt operation .............................................................................................................. 10 ? external interrupt ............. .................................................................................................... 109 ovp interrupt ...................................................................................................................... 109 ? ulti-function interrupt ........................................................................................................ 109 a/d converter interrupt ........................................................................................................ 110 time base interrupts ............................................................................................................ 110 lvd interrupt ........................................................................................................................ 111 t ? interrupts ........................................................................................................................ 111 interrupt wake-up function .................................................................................................. 11 ? programming considerations ............. .................................................................................. 11 ? low voltage detector C lvd .......... .............................................................. 113 lvd register ............. ........................................................................................................... 11 ? lvd operation ...................................................................................................................... 114 application circuits ........... ........................................................................... 115 rev. 1.10 4 ?a? 1?? ?01? rev. 1.10 5 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu instruction set ............................................................................................... 116 introduction .......................................................................................................................... 116 instruction timing ................................................................................................................. 116 ? oving and transferring data .............................................................................................. 116 arithmetic operations ........................................................................................................... 116 logical and rotate operations ............. ................................................................................ 11 ? branches and control transfer ............................................................................................ 11 ? bit operations ...................................................................................................................... 11 ? table read operations ........................................................................................................ 11 ? other operations ............. ..................................................................................................... 11 ? instruction set summary .......... ................................................................... 118 instruction defnition ................................................................................... 120 package information ................................................................................... 129 16-pin ssop (150mil) outline dimensions ......................................................................... 1 ? 9 reel dimensions ................................................................................................................. 1 ? 0 carrier tape dimensions ..................................................................................................... 1 ? 1 rev. 1.10 6 ? a ? 1 ?? ? 01 ? rev. 1.10 ? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu features cpu features ? operating v oltage: f sys =4mhz: 2.2v~5.5v ? up to 1s instruction cycle with 4mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillator: internal 4mhz rc C hirc internal 32khz rc C lirc ? fully integrated internal 4mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 4-level subroutine nesting ? bit manipulation instruction peripheral features ? program memory: 2k16 ? data memory: 1288 ? watchdog t imer function ? 7 bidirectional i/o lines ? one external interrupt line shared with i/o pin ? multiple t imer modules for time measure, input capture, compare match output, pwm output function or single pulse output function ? over voltage protection (ovp) with interrupt ? dual t ime-base functions for generation of fxed time interrupt signals ? 4-channel 12-bit resolution a/d converter ? low voltage reset function (enabled @ 2.1v) ? low voltage detect function ? one integrated ldo: 3v ? 4 level shift output pins ? package type: 16-pin ssop rev. 1.10 6 ?a? 1?? ?01? rev. 1.10 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu general description the device is a flash memory a/d type 8-bit high performance risc architecture microcontroller . offering users the convenience of flash memory multi-programming features, this device also includes a wide range of functions and features. analog fe atures i nclude a m ulti-channel 12-b it a/ d c onverter, a n ove r vol tage prot ection func tion and a ldo regulator . multiple and extremely flexible t imer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal w atchdog t imer, low v oltage r eset a nd l ow v oltage de tector c oupled wi th e xcellent n oise i mmunity a nd e sd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of h irc and lirc os cillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate a nd swi tch d ynamically b etween a r ange o f o perating m odes u sing d ifferent c lock so urces gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vice wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. block diagram ? ?? ?? ? ? - ? ? ? ? ? ? ? ? ? ? ?? ?- -? ?? ? ?? ?? ? ?? ? ? ? ? ? ?? - ? rev. 1.10 8 ? a ? 1 ?? ? 01 ? rev. 1.10 9 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu pin assignment 1 3 2 4 6 5 8 7 9 10 12 11 15 16 13 14 bx cx v12 dx pa0/ovp/an0 vss1 pa1/dapwr/an1/vref vdd/vbf/v5 pa3/tp1_0/outh/an3 pa2/tck2/tp0_1/an2 pa4/tp1_1/outl pa7/tp0_0/icpck/ocdsck pa6/int1/tck1/tp2_1/icpda/ocdsda ax vcc1 vss HT45FH3T 16 ssop-a note: 1. the HT45FH3T i/o lines, pb0/tck3, pb1/tp3, pb2~pb4, are internally connected to the level shift inputs, a, b, c, d and enbf , respectively. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. 3. the p a5/int0/tck0/tp2_0 i/o line is not bonded to the external pin and must be appropriately managed to avoid the power consumption due to the unknown input voltage level. 4. the 16 ssop-a package is for the real ic, the 16 nsop-a package is for the ocds ev ic. pin description with the exceptio n of the power pins and some relevant transformer control pins, all pins on these devices c an be re ferenced by t heir port na me, e .g. p a0, p a1 e tc, whi ch re fer t o t he di gital i/ o function of the pins. however these port pins are also shared with other function such as the analog to digital converter, t imer module pins etc. t he function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. rev. 1.10 8 ?a? 1?? ?01? rev. 1.10 9 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu pin name function opt i/t o/t pin-shared mapping pa0~pa4 ? pa6~pa ? general purpose i/o port a. register enabled pull-up and wake-up papu pawu st c ? os outh ? outl pw ? output t ? pc c ? os pa ?? pa4 ovp over voltage protection input ocvpr1 an pa0 an0~an ? a/d converter input 0~ ? adcr0 acerl an pa0~pa ? vref a/d converter reference voltage input adcr1 an pa1 dapwr d/a converter power input ovpref pwr pa1 int1 external interrupt 1 integ intc ? st pa6 tck0~tck ? t ? 0~t ?? clock input st pa5 ? pa6 ? pa ? tp0_0 ? tp0_1 t ? 0 i/o t ? pc st c ? os pa ?? pa ? tp1_0 ? tp1_1 t ? 1 i/o t ? pc st c ? os pa ?? pa4 tp ? _0 ? tp ? _1 t ?? i/o t ? pc st c ? os pa5 ? pa6 icpck in-circuit programming clock pin st pa ? icpda in-circuit programming data/address pin st c ? os pa6 ocdsck on-chip debug support clock pin st pa ? ocdsda on-chip debug support data/address pin st c ? os pa6 v1 ? level shift output power pwr vbf level shift input power pwr bond with vdd v5 ldo output for ? cu power suppl ? pwr bond with vdd vcc1 ldo positive power suppl ? pwr vss1 ldo negative power suppl ?? ground pwr vdd positive power suppl ? pwr vss negative power suppl ?? ground pwr ax ? bx ? cx ? dx level shift outputs note: the i/o line p a5/int0 is not bonded to the external pin and should be properly confgured after power on reset. the functional pin which is pin-shared with pa5 will lose the corresponding pin function. rev. 1.10 10 ? a ? 1 ?? ? 01 ? rev. 1.10 11 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu internal connection description signal name function opt i/t o/t pin-shared mapping pb0~pb4 general purpose input/output. register enabled pull-up. internall ? connected to the level shift inputs respectivel ? and level shift enable. pbpu st c ? os a ? b ? c ? d level shift inputs. internall ? connected to pb0 ? pb1 ? pb ? and pb ? respectivel ? . enbf level shift enable ? active low. internall ? connected to pb4 note: i/t: input type; o/t: output type opt: optional by confguration option (co) or register option pwr: power; an: analog signal cmos: cmos output; st: schmitt t rigger input absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... .................................................................................... -50 c to 150c operating t emperature .............. ................................................................................... -40 c to 85 c i oh t otal .............. ...................................................................................................................... -80ma i ol t otal .............. ....................................................................................................................... 80ma total power dissipation .............. .......................................................................................... 500mw note: these are stress ratings only . stresses exceeding the range specified under "absolute maximum ratings" may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. rev. 1.10 10 ?a? 1?? ?01? rev. 1.10 11 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4 ? hz ? . ? 5.5 v i dd1 operating current ? normal ? ode ? f sys =f h ? v no load ? f h =4 ? hz ? adc off ? wdt enable 400 600 a 5v 840 1 ? 00 a i dd ? operating current ? slow ? ode ? f sys =f l =lirc ? v no load ? f sys =lirc ? adc off ? wdt enable 10 ? 0 a 5v ? 0 ? 5 a i idle0 idle0 ? ode standb ? current (lirc on) ? v no load ? adc off ? wdt enable ? lvr disable 1.5 ? .0 a 5v ? .5 5.0 a i idle1 idle1 ? ode standb ? current ? v no load ? adc off ? wdt enable ? f sys =4 ? hz on 1 ? 0 ? 60 a 5v ?? 0 500 a i sleep0 sleep0 ? ode standb ? current (lirc off) ? v no load ? adc off ? wdt disable ? lvr disable 0.1 1.0 a 5v 0. ? ? .0 a i sleep1 sleep1 ? ode standb ? current (lirc on) ? v no load ? adc off ? wdt enable ? lvr disable 1.5 ? .0 a 5v ? .5 5.0 a v il1 input low voltage for i/o ports or input pins 5v 0 1.5 v 0 0. ? v dd v v ih1 input high voltage for i/o ports or input pins 5v ? .5 5.0 v 0.8v dd v dd v i ol i/o port sink current ? v v ol =0.1v dd 4 8 ma 5v v ol =0.1v dd 10 ? 0 ma i oh i/o port source current ? v v oh =0.9v dd - ? -4 ma 5v v oh =0.9v dd -5 -10 ma r ph pull-high resistance for i/o ports ? v ? 0 60 100 k 5v 10 ? 0 50 k ote lvr is aways enabled alt mode disabled) fed 2.1v. rev. 1.10 1 ? ? a ? 1 ?? ? 01 ? rev. 1.10 1? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock ? . ? v~5.5v dc 8 ? hz f sys s ? stem clock (hirc) ? . ? v~5.5v 8 ? hz f hirc hirc frequenc ? (note) ? v ta= ? 5c - ? % 4 + ? % ? hz ? .4 v ~ ? .6v ta=0c~ ? 0c -5% 4 +5% ? hz ? .4 v ~ ? .6v ta=-40c ~85c -10% 4 +10% ? hz f lirc s ? stem clock (lirc) 5v ta= ? 5c -10% ?? +10% khz ? . ? v~5.5v ta=-40c ~85c - ? 0% ?? +60% khz t ti ? er tckn input pin ? inimum pulse width ? 0 ns t int interrupt ? inimum pulse width 1 ? . ? 5 s t sst s ? stem start-up timer period (wake-up from halt ? f sys off at halt state) f sys =hirc 16 t sys f sys =lirc ? t sys s ? stem start-up timer period (wake-up from halt ? f sys on at halt state) ? t sys t rstd s ? stem reset dela ? time (power on reset ? lvr ? wdtc/lvrc sw reset) ? 5 50 100 ms s ? stem reset dela ? time (wdt time-out reset) 8. ? 16. ? ?? . ? ms 1rwh w sys i sys dd h dffudf i h hudo foodu iuhthf d hfso fdsdfu o be fhfh hhh d d ofdh d foh h hyfh d soh a/d converter electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v adi a/d converter input voltage 0 v ref v v ref a/d converter reference voltage ? v dd v v bg reference voltage - ? % 1.19 + ? % v dnl differential non-linearit ? 5v t adck =1.0s 1 ? lsb inl integral non-linearit ? 5v t adck =1.0s ? 4 lsb i adc additional power consumption if a/d converter is used ? v no load (t adck =0.5s ) 0.9 1. ? 5 ma 5v no load (t adck =0.5s ) 1. ? 1.8 ma i bg additional power consumption if v bg reference with buffer is used ? 00 ? 00 a t adck a/d converter clock period 0.5 10 s t adc a/d conversion time (include sample and hold time) 1 ? bit adc 16 t adck t ads a/d converter sampling time 4 t adck t on ? st a/d converter on-to-start time ? s t bgs v bg turn on stable time ? 00 s rev. 1.10 1? ?a? 1?? ?01? rev. 1.10 1 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu lvd & lvr electrical characteristics ta= ? 5 c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr low voltage reset voltage lvr enable -5%t ? p. ? .1 +5%t ? p. v v lvd1 low voltage detector voltage lvden=1 ? v lvd = ? . ? v -5% t ? p. ? . ? +5% t ? p. v v lvd ? lvden=1 ? v lvd = ? .4v ? .4 v v lvd ? lvden=1 ? v lvd = ? . ? v ? . ? v v lvd4 lvden=1 ? v lvd = ? .0v ? .0 v v lvd5 lvden=1 ? v lvd = ? . ? v ? . ? v v lvd6 lvden=1 ? v lvd = ? .6v ? .6 v v lvd ? lvden=1 ? v lvd =4.0v 4.0 v i lvr low voltage reset current lvr enable ? lvden=0 ? 0 ? 0 a i lvd low voltage detector current lvr enable ? lvden=1 ? 0 45 a t lvr low voltage width to reset 1 ? 0 ? 40 480 s t lvd low voltage width to interrupt ? 0 45 90 s t lvds lvdo stable time for lvr enable, lvd offon 15 s for lvr disable, lvd offon ? 00 s t sreset software reset width to reset 45 90 1 ? 0 s ote lvr is aways enabled alt mode disabled) fed 2.1v. ldo regulator characteristics v5= ? v ? v in =v out + 1.0v ? i o =1ma, ta=25c, unless otherwise specifed symbol parameter test conditions min. typ. max. unit v dd conditions v out output voltage tolerance i o =10ma ? ta= ? 5 c - ? ? % v load load regulation (note 1) 1mai o 30ma, v in =5v 0.09 0.18 %/ma 1mai o 12ma, v in =4v v drop drop out voltage (note ? ) i o = ? ma ? v o = ? % ?? 0 mv i o =5ma ? v o = ? % 450 mv i ss quienscent current i o =0ma ? 4 a v line line regulation ? .0v+v out v in 28v, i o =1ma 0. ? %/v v in input voltage v cc ? 8 v v out /ta temperature coeffcient i o =10ma ? -40 c rev. 1.10 14 ?a? 1?? ?01? rev. 1.10 15 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu oscillator temperature/frequency characteristics the f ollowing c haracteristic g raphics d epicts t ypical o scillator b ehavior. t he d ata p reseted h ere i s a statistic al summary of data gathered on units from dif ferent lots over a period of time. this is for information only and the fgures were not tested during manufacturing. in some of the graphs, the data exceeding the specifed operating range are shown for information purposes only. the device will operate properly only within the specifed range. hirc -- 4mhz (3v) 3.7000 3.7500 3.8000 3.8500 3.9000 3.9500 4.0000 4.0500 4.1000 4.1500 -60 -40 -20 0 20 40 60 80 100 ta( ) f sys (mhz) 2.2v 2.3v 2.4v 2.5v 2.7v 3v 3.3v 3.6v rev. 1.10 16 ? a ? 1 ?? ? 01 ? rev. 1.10 1? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device take s advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal regis ters are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control syst em wi th ma ximum reli ability and flexi bility. thi s ma kes t he devic e suit able for low-cost, high-volume production for controller applications. clocking and pipelining the m ain syst em c lock, de rived from e ither an hirc or l irc osc illator i s subdi vided i nto four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. ? ? ? ? ? system clock and pipelining rev. 1.10 16 ?a? 1?? ?01? rev. 1.10 1 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is e xecuted e xcept f or i nstructions, su ch a s jmp o r call t hat d emand a j ump t o a non-consecutive pr ogram me mory a ddress. on ly t he l ower 8 b its, k nown a s t he pr ogram c ounter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc10~pc8 pcl ? ~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. rev. 1.10 18 ? a ? 1 ?? ? 01 ? rev. 1.10 19 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.10 18 ?a? 1?? ?01? rev. 1.10 19 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, th is flash device of fer s users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 2k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. 000h initialisation vector 004h 7ffh 16 bits external interrupt 0 vector over voltage protection interrupt multi function interrupt 0 vector 008h 00ch 010h multi function interrupt 1 vector multi function interrupt 2 vector multi function interrupt 3 vector 014h 018h multi function interrupt 4 vector 01ch 020h a/d converter interrupt vector time base 0 interrupt vector 024h time base 1 interrupt vector 028h external interrupt 1 vector 02ch look-up table n00h nffh program memory structure rev. 1.10 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.10 ?1 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd [m] or t abrdl [m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table. instruction table location bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd [m] @10 @9 @8 @ ? @6 @5 @4 @ ? @ ? @1 @0 tabrdl [m] 1 1 1 @ ? @6 @5 @4 @ ? @ ? @1 @0 table location note: b10~b0 : t able location bits @7~@0: t able pointer (tblp) bits @10~@8: t able pointer (tbhp) bits rev. 1.10 ?0 ?a? 1?? ?01? rev. 1.10 ? 1 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : rev. 1.10 ?? ? a ? 1 ?? ? 01 ? rev. 1.10 ?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek writer pins mcu programming pins pin description icpda pa6 programming serial data/address icpck pa ? programming clock vdd vdd power suppl ? vss vss ground the program memory can be programmed serially in-circuit using this 4-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional l ines a re r equired f or t he p ower su pply. t he t echnical d etails r egarding t he i n-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during the programming proces s, taking control of the p a6 and p a7 pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. rev. 1.10 ?? ?a? 1?? ?01? rev. 1.10 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu on-chip debug support C ocds there is an ev chip which is used to emulate the device. the ev chip device also provides an on-chip de bug fu nction t o de bug t he de vice du ring t he de velopment pr ocess. t he e v c hip and t he a ctual mcu de vices a re a lmost funct ionally c ompatible e xcept for on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, other functions which are shared with the ocdsda and ocdsck pins in the actual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip debug support data/address input/output ocdsck ocdsck on-chip debug support clock input vdd vdd power suppl ? gnd vss ground ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. rev. 1.10 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.10 ?5 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu 00h iar 0 01h ?p 0 0?h iar 1 0?h ?p 1 04h 05h acc 06h pcl 0?h tblp 08h tblh 09h tbhp 0 ah status 0 bh s?od 0 ch lvdc 0 dh integ 0 eh 0 fh 10h intc 0 11h intc 1 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh pa pac : unused 1?h 14h ?fi 0 15h ?fi 1 16h 1?h : unused ? read as 00h intc ? ?fi ? pbc wdtc tbc pbpu pb ctrl adrl adrh adcr 0 adcr 1 acerl unused t? 0c0 t? 0c1 t? 0 dl t? 0 dh t? 0 al t? 0 ah t? 0 rpl t? 1c0 t? 1c1 ?0h ?1h ??h ?9h ?8h ? bh ? ah ? dh ? ch ? fh ? eh ??h ?4h ?5h ?6h ??h ?0 h ?1 h ?? h ?8 h ? dh ? ch ? fh ? eh ?? h ?4 h ?5 h ?6 h ?? h t? 1 dl t? 1 dh t? 1 al t? 1 ah ovpref t? ?c0 t? ?c1 t? ? dl t? ? dh t? ? al t? ? ah 40 h 41 h 4? h 4? h 44 h 45 h 46 h 4? h 48 h 49 h 4 ah 4 bh 4 ch 4 dh 4 eh 4 fh unused 50 h 51 h 5? h 5? h 54 h : ? fh unused ?fi ? ?fi 4 t?pc unused lvrc t? 0 rph t? 1 rpl t? 1 rph : ocvpr 0 ocvpr 1 ocvpr ? cpr unused unused t? ?c0 t? ?c1 t? ? dl t? ? dh t? ? al t? ? ah unused : : : : : : special purpose data memory structure 00h ?fh 80h ffh special purpose data ?emor? general purpose data ?emor? data memory structure rev. 1.10 ?4 ?a? 1?? ?01? rev. 1.10 ? 5 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is directed to is the address specifed by the related memory pointer. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. rev. 1.10 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.10 ?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, whe n t ransferring da ta be tween one user - defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter s a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. rev. 1.10 ?6 ?a? 1?? ?01? rev. 1.10 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 "" unknown bit 7~6 unimplemented, read as "0" bit 5 to: w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.10 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.10 ?9 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options an d registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the watchdog t imer and t ime base interrupts. f ully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. internal high speed rc hirc 4 ? hz internal low speed rc lirc ?? khz oscillator types system clock confgurations there are t wo m ethods of generat ing t he syst em cl ock, a high spee d osci llator and a low spee d oscillator. the high s peed os cillator is the internal 4m hz rc os cillator C h irc. the low s peed oscillator is the internal 32khz (lirc) oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for the high speed and the low speed oscillators is chosen via registers . the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bi ts i n t he smod re gister. not e t hat t wo osc illator se lections m ust be m ade na mely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. high speed oscillator hirc lirc low speed oscillator f h 6-stage prescaler hlclk? cks?~cks0 bits f h /? f h /4 f h /8 f h /16 f h /?? f h /64 f sub f sys system clock confgurations rev. 1.10 ?8 ?a? 1?? ?01? rev. 1.10 ? 9 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal rc o scillator h as a f ixed f requency o f 4 mhz. de vice t rimming d uring t he manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operation . internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from the hirc oscillator . the low speed system clock source can be sourced from t he l irc osc illator. t he ot her c hoice, wh ich i s a di vided ve rsion of t he hi gh spe ed system oscillator has a range of f h /2~f h /64. rev. 1.10 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.10 ?1 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ? ? ? ? ? ? ? - ? ? ?? - ?? ? ? system clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. rev. 1.10 ?0 ?a? 1?? ?01? rev. 1.10 ? 1 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, the normal mode and slow mode. the remainin g three modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f sub f tbc n or ? al mode on f h ~f h /64 on on slow mode on f sub on on ilde0 mode off off on on idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . this mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod regis ter. a lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock so urce. t he c lock so urce u sed wi ll b e f rom f sub . r unning t he m icrocontroller i n t his m ode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f sub clock will be stopped too, and the w atchdog t imer function is disabled. in this mode, the lvden is must set to 0. if the lvden is set to 1, it wont enter the sleep0 mode. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however the f sub clock will continue to operate if the lvden is 1 or the w atchdog t imer function is enabled. idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu, the system oscillator will be stopped, the low frequency clock f sub will be on. rev. 1.10 ?? ? a ? 1 ?? ? 01 ? rev. 1.10 ?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator . in the idle1 mode the low frequency clock f sub will be on. note: if l vden=1 and the sleep or idle mode is entered, the l vd and bandgap functions will not be disabled, and the f sub clock will be forced to enable. control register the smod register is used to control the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 lto hto idlen hlclk r/w r/w r/w r/w r r r/w r/w por 1 1 0 0 0 1 0 b it 7~5 cks2~cks0 : the system clock selection when hlclk is 0 000: f sub 001: f sub 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0. b it 3 lto : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscill ator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will change to a high level after 1~2 cycles. b it 2 hto : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscillator sst ready fag which indicates when the high speed system oscillator is stable after a wake-up has occurred. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the h igh sp eed sy stem o scillator i s stable. t herefore t his fag wi ll a lways b e r ead a s 1 by the application program after device power -on. the fag will be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 15~16 clock cycles if the hirc oscillator is used. rev. 1.10 ?? ?a? 1?? ?01? rev. 1.10 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu b it 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. b it 0 hlclk : system clock selection 0: f h /2~f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f sub clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f sub clock will be selected. when system clock switches from the f h clock to the f sub clock and the f h clock will be automatically switched off to conserve power. ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 b it 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0. bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. t his bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application program. note that this bit can only be cleared to 0 by the application program. rev. 1.10 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.10 ?5 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ?? ? ? ? ? ? ? ? operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent tas k in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow mode s t o t he sl eep/idle mode s i s e xecuted vi a t he hal t i nstruction . when a hal t instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f sub . if the clock is from the f sub , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal cloc k sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying fowchart shows what happens when the device moves between the various operating modes. rev. 1.10 ?4 ?a? 1?? ?01? rev. 1.10 ? 5 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power , the system clock can switch to run in the slow mode by setting the hlclk bit to 0 and setting the cks2~cks0 bits to 000b or 001b in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto b it i s c hecked. t he a mount o f t ime r equired f or h igh sp eed sy stem o scillator st abilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the sleep1 mode there is only one way for the devic e to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt or l vd on. w hen t his i nstruction i s e xecuted unde r t he c onditions de scribed a bove, t he following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.10 ?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the hal t instruc tion, but the t ime base clock f tbc and the w atchdog t imer clock f s will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock together with the t ime base clock f tbc and the w atchdog t imer clock f sub will be on and the application program will stop at the halt instruc tion. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting . ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. rev. 1.10 ?6 ?a? 1?? ?01? rev. 1.10 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? -?? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?? ?? ? -?? ? ? ? ? ?? ?? ? -?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? -?? ? rev. 1.10 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.10 ?9 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow i f the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. t he actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a sys tem power -up or executing the clear w atchdog t imer instructions and is set w hen executing the h alt ins truction. the t o flag is s et if a wd t time-out occurs , and causes a wake-up that only resets the program counter and stack pointer , the other flags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. rev. 1.10 ?8 ?a? 1?? ?01? rev. 1.10 ? 9 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal f s clock which is in turn supplied by the lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 t o 2 18 t o gi ve l onger t imeouts, t he a ctual va lue be ing c hosen usi ng t he w s2~ws0 bi ts i n t he w dtc register. the lirc internal oscillato r has an approximate period of 32khz at a supply voltage of 5v . however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. the wdtc register is initiated to 0101001 1b at any reset but keeps unchanged at the wdt time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we ? we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 we4~we0 : wdt function software control 10101: disabled 01010: enabled other: reset mcu when these bits are changed by the environmental noise to reset the microcontroller , the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1. bit 2~0 ws2~ws0 : wdt t ime-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub rev. 1.10 40 ? a ? 1 ?? ? 01 ? rev. 1.10 41 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson: f sys control in idle mode describe elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf: lvr function reset fag describe elsewhere. bit 1 lrf: lvr control register software reset fag describe elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the w dt control register software reset and c leared by the application program. note that this bit can only be cleared to 0 by the application program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instruction will not be executed in the correct manne r, in which case the w atchdog t imer will overfow and reset the device. there are fve bits, we4~we0, in the wdtc register to enable/disable the wdt function. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b while the wdt function will be enable d if the we4~we0 bits are equal to 01010b. however , if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. we4~we0 bits wdt function 10101b disable 01010b enable an ? other value reset ? cu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value is written into the we4~we0 bit fled except 01010b a nd 10101b, t he se cond i s usi ng t he w atchdog t imer soft ware c lear i nstructions a nd t he third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. rev. 1.10 40 ?a? 1?? ?01? rev. 1.10 41 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu clr wdtinstruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset ?cu lirc f sub f sub /? 8 8-to-1 ?ux clr ws?~ws0 (f sub /? 8 ~ f sub /? 18 ) wdt time-out (? 8 /f sub ~ ? 18 /f sub ) watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the watchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur, through events occurring internally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. vdd power-on reset sst time-out t rstd note: t rstd is power-on delay, typical time=50ms power-on reset timing chart rev. 1.10 4 ? ? a ? 1 ?? ? 01 ? rev. 1.10 4? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low su pply v oltage st ate d oes n ot e xceed t his v alue, t he l vr wi ll i gnore t he l ow su pply v oltage and will not perform a reset function. the actual v lvr is fxed at a voltage value of 2.1v by the lvs bits in the l vrc register . if the l vs7~lvs0 bits are changed to some certain values by the environmental noise, the l vr will reset the device after 2~3 lirc cloc k cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode. note: t rstd is power-on delay, typical time=16.7ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs ? lvs6 lvs5 lvs4 lvs ? lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0: lvr voltage select 01010101: 2.1v 00110011: 2.1v 10011001: 2.1v 10101010: 2.1v any other value: generates mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by the above defned l vr voltage value, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles . in this s ituation this regis ter contents w ill remain the same after such a reset occurs. any register value, other than the four defined values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation this register contents will be reset to the por value. rev. 1.10 4? ?a? 1?? ?01? rev. 1.10 4 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson: f sys control in idle mode describe elsewhere. bit 6~3 unimplemented, read as "0" bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. t his bit can only be cleared to 0 by the application program. bit 0 wrf: wdt control register software reset fag describe elsewhere. watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a lvr reset except that the watchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep1 or idle mode the w atchdog time-out reset during sleep1 or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 16 clock cycles if the system clock source is provided by the hirc. the t sst is 2 clock for the lirc. wdt time-out reset during sleep1 or idle timing chart rev. 1.10 44 ? a ? 1 ?? ? 01 ? rev. 1.10 45 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during nor ? al or slow ? ode operation 1 u wdt time-out reset during nor ? al or slow ? ode operation 1 1 wdt time-out reset during idle or sleep1 ? ode operation u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset ? wdt begins counting timer ? odules timer ? odules will be turned off input/output ports i/o ports will be setup as inputs and an0~an ? as a/d input pins stack pointer stack pointer will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. rev. 1.10 44 ?a? 1?? ?01? rev. 1.10 45 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu register power on reset wdt time-out (normal operation) lvr reset wdt time-out (idle/sleep1 mode) ? p0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ? p1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu ---- -uuu status --00 xxxx --1u uuuu --uu uuuu --11 uuuu s ? od 110- 0010 110- 0010 110- 0010 uuu- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc ? 0000 0000 0000 0000 0000 0000 uuuu uuuu ? fi0 --00 --00 --00 --00 --00 --00 --uu --uu ? fi1 --00 --00 --00 --00 --00 --00 --uu --uu ? fi ? --00 --00 --00 --00 --00 --00 --uu --uu ? fi ? --00 --00 --00 --00 --00 --00 --uu --uu ? fi4 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb ---1 1111 ---1 1111 ---1 1111 ---u uuuu pbc ---1 1111 ---1 1111 ---1 1111 ---u uuuu pbpu ---0 0000 ---0 0000 ---0 0000 ---u uuuu t ? pc 0000 0000 0000 0000 0000 0000 uuuu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 uuuu -uuu adrl(adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl(adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 --00 0110 --00 0110 --00 uuuu --uu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu acerl ---- 1111 ---- 1111 ---- 1111 ---- uuuu ctrl 0--- -x00 0--- -000 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu t ? 0c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- t ? 0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0dh 0000 0000 0000 0000 0000 0000 0000 uuuu t ? 0al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0ah 0000 0000 0000 0000 0000 0000 0000 uuuu t ? 0rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 0rph 0000 0000 0000 0000 0000 0000 0000 uuuu t ? 1c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- rev. 1.10 46 ? a ? 1 ?? ? 01 ? rev. 1.10 4? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu register power on reset wdt time-out (normal operation) lvr reset wdt time-out (idle/sleep1 mode) t ? 1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1dh ---- --00 ---- --00 ---- --00 ---- --uu t ? 1al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1ah ---- --00 ---- --00 ---- --00 ---- --uu t ? 1rpl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ? 1rph ---- --00 ---- --00 ---- --00 ---- --uu t ?? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dh ---- --00 ---- --00 ---- --00 ---- --uu t ?? al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? ah ---- --00 ---- --00 ---- --00 ---- --uu t ?? c0 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? c1 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dl 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? dh ---- --00 ---- --00 ---- --00 ---- --uu t ?? al 0000 0000 0000 0000 0000 0000 uuuu uuuu t ?? ah ---- --00 ---- --00 ---- --00 ---- --uu cpr ---0 0000 ---0 0000 ---0 0000 ---u uuuu ovpref 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu ocvpr0 -0-- 00-0 -0-- 00-0 -0-- 00-0 -u-- uu-u ocvpr1 -011 x-00 -011 x-00 -011 x-00 -uuu u-uu ocvpr ? 0010 0000 0010 0000 0010 0000 uuuu uuuu note: "-" stands for un implemented "u" stands for "unchanged" "x" stands for "unknown" rev. 1.10 46 ?a? 1?? ?01? rev. 1.10 4 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a and pb. these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa d ? d6 d5 d4 d ? d ? d1 d0 pac d ? d6 d5 d4 d ? d ? d1 d0 papu d ? d6 d5 d4 d ? d ? d1 d0 pawu d ? d6 d5 d4 d ? d ? d1 d0 pb d4 d ? d ? d1 d0 pbc d4 d ? d ? d1 d0 pbpu d4 d ? d ? d1 d0 i/o resistor lists pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers p apu~pbpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7~0 i/o port a bit 7~bit 0 pull-high control 0: disable 1: enable pbpu register bit 7 6 5 4 3 2 1 0 name d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~5 unimplemented, read as "0" b it 4~0 i/o port b bit 4 ~bit 0 pull-high control 0: disable 1: enable rev. 1.10 48 ? a ? 1 ?? ? 01 ? rev. 1.10 49 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 b it 7~0 i/o port a bit 7~bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~pbc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 b it 7~0 i/o port a bit 7~bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 name d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 bit 7~5 unimplemented, read as "0" b it 4~0 i/o port b bit 4~ bit 0 input/output control 0: output 1: input rev. 1.10 48 ?a? 1?? ?01? rev. 1.10 49 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. ?? ? ?? ? ? ? generic input/output structure ? ? ? ? ? ? - ? ? ? ? ? ? ?? - a/d input/output structure rev. 1.10 50 ? a ? 1 ?? ? 01 ? rev. 1.10 51 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, p ac~pbc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pb, are frst programmed. selecting which pins are inputs and which are outputs c an b e a chieved b yte-wide b y l oading t he c orrect v alues i nto t he a ppropriate p ort c ontrol register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcon troller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. read/wite timing port a has the additional capability of providing wake-up functions. when the device is in the sleep or id le m ode, various methods are available to w ake the device up. o ne of thes e is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure t ime. t o i mplement t ime r elated f unctions t he d evice i ncludes se veral t imer mo dules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as t imer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has two individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual periodic and compact tm sections. introduction the device contains four tms with each tm having a reference name of tm0, tm1, tm2 and tm3. the tm0 and tm1 are 16-bit and 10-bit periodic t ype tms (ptm) respectively while the tm2 and tm3 are 10-bit compact t ype tms (ctm). the common features to the periodic and compact tms will be described in this section and the detailed operation will be described in corresponding section. the main features of the compact and periodic tms are summarised in the accompanying table. rev. 1.10 50 ?a? 1?? ?01? rev. 1.10 51 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu function ctm ptm timer/counter i/p capture compare ? atch output pw ? channels 1 1 single pulse output 1 pw ? alignment edge edge pw ? adjustment period & dut ? dut ? or period dut ? or period tm function summary tm0 tm1 tm2 tm3 16-bit pt ? 10-bit pt ? 10-bit ct ? 10-bit ct ? tm name/type reference tm operation the two different t ypes o f t m s o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input in ef fect disconnecting the tm clock source except the clock source selection for tm1. the tckn pin clock source is used to allow an exter nal signal to drive the tm as an external clock source or for event counting. tm interrupts the periodic and compact type tms both have two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. rev. 1.10 5 ? ? a ? 1 ?? ? 01 ? rev. 1.10 5? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each ha ve one or more output pins. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must firs t be setup using registers. a single bit in one of the registers determines if its associated pi n i s t o be use d a s a n e xternal t m out put pi n or i f i t i s t o ha ve a nother func tion. the number of output pins for each tm type is dif ferent, the details are provided in the accompanying table. the tm output pin names have a _n suffx. pin names that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. tm0 tm1 tm2 tm3 register tp0_0 ? tp0_1 tp1_0 ? tp1_1 tp ? _0 ? tp ? _1 tp ? t ? pc tm output pins tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using the control register , with a single bit in the register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. rev. 1.10 5? ?a? 1?? ?01? rev. 1.10 5 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm0 function pin control block diagram tm 1 function pin control block diagram rev. 1.10 54 ? a ? 1 ?? ? 01 ? rev. 1.10 55 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm2 function pin control block diagram tm3 function pin control block diagram rev. 1.10 54 ?a? 1?? ?01? rev. 1.10 55 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tmpc register bit 7 6 5 4 3 2 1 0 name outcp1 outcp0 t ? 1cp1 t ? cp0 t1cp1 t1cp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 outcp [1:0]: outh and outl pin control 00: normal i/o function, i.e., pa3 and pa4 01: outh and pa4 10: pa3 and outl 11: outh and outl if thes e bits are set to 1 1, the dead time circuitry w ill be automatically enabled. if t hese bi ts a re se t t o a va lue e xcept 11, t hen t he de ad t ime c ircuitry wi ll be automatically disabled. bit 5 t2cp1: tp2_1 pin control 0: tp2_1 pin is disabled 1: tp2_1 pin is enabled bit 4 t2cp0: tp2_0 pin control 0: tp2_0 pin is disabled 1: tp2_0 pin is enabled bit 3 t1cp1: tp1_1 pin control 0: tp1_1 pin is disabled 1: tp1_1 pin is enabled bit 2 t1cp0: tp1_0 pin control 0: tp1_0 pin is disabled 1: tp1_0 pin is enabled bit 1 t0cp1: tp0_1 pin control 0: tp0_1 pin is disabled 1: tp0_1 pin is enabled bit 0 t0cp0: tp0_0 pin control 0: tp0_0 pin is disabled 1: tp0_0 pin is enabled rev. 1.10 56 ? a ? 1 ?? ? 01 ? rev. 1.10 5? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu programming considerations the tm counter registers, the capture/compare ccra registers and the ccrp registers, being either 16-bit or 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specific way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrp registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra or ccrp low byte registers, named tmxal or tmxrpl, using the following access procedures. accessing the ccra or ccrp low byte register without following these access procedures will result in unpredictable values. ? ? ? the following steps show the read and write procedures: ? writing data to ccra or ccrp ? step 1. w rite data to low byte tmxal or tmxrpl C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxrph C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra or ccrp ? step 1. read data from the high byte tmxdh, tmxah or tmxrph C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxrpl C this step reads data from the 8-bit buffer. rev. 1.10 56 ?a? 1?? ?01? rev. 1.10 5 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu compact type tm C ctm (tm2, tm3) although the simplest form of the tm types, the compact tm type still contains three operating modes, wh ich a re c ompare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. name tm no. tm input pin tm output pin 10-bit ct ? ?? ? tck ?? tck ? tp ? _0 ? tp ? _1; tp ? compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changi ng the value of the 10-bit count er using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - - ? ??? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram (n=2 or 3) note: for tm3 there is only one tm output signal named tp3 and the tp3. rev. 1.10 58 ? a ? 1 ?? ? 01 ? rev. 1.10 59 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu compact type tm register description overall operat ion of t he compa ct tm i s cont rolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t ? nc0 tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 t ? nc1 tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tndpx tncclr t ? ndl d ? d6 d5 d4 d ? d ? d1 d0 t ? ndh d9 d8 t ? nal d ? d6 d5 d4 d ? d ? d1 d0 t ? nah d9 d8 compact tm register list (n=2 or 3) tmndl register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 rev. 1.10 58 ?a? 1?? ?01? rev. 1.10 59 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8 tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tnon tnrp ? tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the undefned clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falli ng edge . the clock source f sys is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop t he c ounter f rom c ounting a nd t urn o ff t he t m wh ich wi ll r educe i ts p ower consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. rev. 1.10 60 ? a ? 1 ?? ? 01 ? rev. 1.10 61 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu bit 2~0 tnrp2~tnrp0: tmn ccrp 3-bit register, compare with the tmn counter bit 9~bit 7 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are t hen c ompared wi th t he i nternal c ounter's h ighest t hree b its. t he r esult o f t his comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tmnc1 register bit 7 6 5 4 3 2 1 0 name tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0: select tmn operation mode 00: compare match output mode 01: capture input mode 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn_0, tpn_1 or tpn output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused. these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. rev. 1.10 60 ?a? 1?? ?01? rev. 1.10 61 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 tnoc: tpn_0, tpn_1 or tpn output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn_0, tpn_1 or tpn output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0, tpn_1 or tpn output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tndpx: tmn pwm period/duty control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode or input capture mode. rev. 1.10 6 ? ? a ? 1 ?? ? 01 ? rev. 1.10 6? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu compact type tm operation modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. rev. 1.10 6? ?a? 1?? ?01? rev. 1.10 6 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value 0 x? f f ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf t? o / p pin time ccrp =0 ccrp > 0 counter overflow ccrp > 0 counter cleared b? ccrp value pause resume stop counter restart tncclr = 0 ; tn? [1:0 ] = 00 output pin set to initial level low if tnoc =0 output toggle with tnaf flag note tnio [1:0 ] = 10 active high output select here tnio [1:0 ] = 11 toggle output select output not affected b? tnaf flag . remains high until reset b? tnon bit output pin reset to initial value output controlled b? other pin - shared function output inverts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin controlled only by tnaf fag 3. the output pin is reset to its initial state by tnon bit rising edge rev. 1.10 64 ? a ? 1 ?? ? 01 ? rev. 1.10 65 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared b? ccra value pause resume stop counter restart tncclr = 1; tn? [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected b? tnaf flag. remains high until reset b? tnon bit output pin reset to initial value output controlled b? other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by tnaf fag 3. the tm output pin is reset to initial state by tnon rising edge 4. the tnpf fags is not generated when tncclr=1 rev. 1.10 64 ?a? 1?? ?01? rev. 1.10 65 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 56 ? 84 51 ? 640 ? 68 896 10 ? 4 dut ? ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra dut ? 1 ? 8 ? 56 ? 84 51 ? 640 ? 68 896 10 ? 4 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value. rev. 1.10 66 ? a ? 1 ?? ? 01 ? rev. 1.10 6? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tn? [1:0] = 10 pw? dut? c?cle set b? ccra pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccrp t? o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio1, tnio0=00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.10 66 ?a? 1?? ?01? rev. 1.10 6 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tn? [1:0] = 10 pw? dut? c?cle set b? ccrp pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccra t? o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.10 68 ? a ? 1 ?? ? 01 ? rev. 1.10 69 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu periodic type tm C ptm (tm0, tm1) the periodic t ype tm contains five operating modes, which are compare match output, timer/event counter , capture input, single pulse output and pwm output modes. the periodic tm can also be controlled with an external input pin and can drive one external output pin. periodic tm operation there are two sizes of periodic tms, one is 10-bit wide and the other is 16-bit wide. at its core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are two internal comparators with the names, comparato r a and comparator p . these comparators will compare the value in the counter with the ccra and ccrp registers. the o nly wa y o f c hanging t he v alue o f t he 1 0 o r 1 6-bit c ounter u sing t he a pplication p rogram, i s to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the periodic type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pin. all operating setup conditions are selected using relevant internal registers. ? ? ? ? ? ? ? ?? - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16-bit periodic type tm block diagram (n=0) rev. 1.10 68 ?a? 1?? ?01? rev. 1.10 69 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ? ? ? ? ? ? ?? ? - ? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? 10-bit periodic type tm block diagram (n=1) periodic type tm register description overall operation of the periodic tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while two read/write register pairs exist to store the internal 10 or 16-bit ccra and ccrp val ue. the remaining two registers are control registers which setup the different operating and control modes. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t ? nc0 tnpau tnck ? tnck1 tnck0 tnon t ? nc1 tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tncapts tncclr t ? ndl d ? d6 d5 d4 d ? d ? d1 d0 t ? ndh d15 d14 d1 ? d1 ? d11 d10 d9 d8 t ? nal d ? d6 d5 d4 d ? d ? d1 d0 t ? nah d15 d14 d1 ? d1 ? d11 d10 d9 d8 t ? nrpl d ? d6 d5 d4 d ? d ? d1 d0 t ? nrph d15 d14 d1 ? d1 ? d11 d10 d9 d8 16-bit periodic tm register list (n=0) name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 t ? nc0 tnpau tnck ? tnck1 tnck0 tnon t ? nc1 tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tncapts tncclr t ? ndl d ? d6 d5 d4 d ? d ? d1 d0 t ? ndh d9 d8 t ? nal d ? d6 d5 d4 d ? d ? d1 d0 t ? nah d9 d8 t ? nrpl d ? d6 d5 d4 d ? d ? d1 d0 t ? nrph d9 d8 10-bit periodic tm register list (n=1) rev. 1.10 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.10 ?1 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm0c0 register C 16-bit ptm (n=0) bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the undefned clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falli ng edge . the clock source f sys is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop t he c ounter f rom c ounting a nd t urn o ff t he t m wh ich wi ll r educe i ts p ower consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as 0 rev. 1.10 ?0 ?a? 1?? ?01? rev. 1.10 ? 1 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm1c0 register C 10-bit ptm (n=1) bit 7 6 5 4 3 2 1 0 name tnpau tnck ? tnck1 tnck0 tnon r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 tnpau: tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0: select tmn counter clock 000: f sys /4 001: f h 010: f h /16 011: f h /64 100: f tbc 101: f h 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the undefned clock input will ef fectively disable the internal counter . the external pin clock source can be chosen to be act ive on the rising or falli ng edge . the clock source f sys is the system c lock, wh ile f h a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section. bit 3 tnon: tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop t he c ounter f rom c ounting a nd t urn o ff t he t m wh ich wi ll r educe i ts p ower consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 unimplemented, read as 0 rev. 1.10 ?? ? a ? 1 ?? ? 01 ? rev. 1.10 ?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm0c1 register C 16-bit ptm; tm1c1 register C 10-bit ptm (n=0, 1) bit 7 6 5 4 3 2 1 0 name tn ? 1 tn ? 0 tnio1 tnio0 tnoc tnpol tncapts tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0: select tmn operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the tnm1 and tnm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0: select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tpn_0, tpn_1 01: input capture at falling edge of tpn_0, tpn_1 10: input capture at falling/rising edge of tpn_0, tpn_1 11: input capture disabled timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t nio1 a nd t nio0 bi ts de termine how t he tm out put pin changes sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register . note that the output level requested by the tnio1 and tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. rev. 1.10 ?? ?a? 1?? ?01? rev. 1.10 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu bit 3 tnoc: tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol: tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 tncapts: tmn capture trigger source select 0: from tpn_0 or tpn_1 pin 1: from tckn pin bit 0 tncclr: select tmn counter clear condition 0: tmn comparator p match 1: tmn comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he periodic t m c ontains t wo c omparators, com parator a a nd com parator p , e ither of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode, single pulse or input capture mode. tm0dl register C 16-bit ptm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0 counter low byte register bit 7~bit 0 tm0 16-bit counter bit 7~bit 0 rev. 1.10 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.10 ?5 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm1dl register C 10-bit ptm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm0dh register C 16-bit ptm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0 counter high byte register bit 7~bit 0 tm0 16-bit counter bit 15~bit 8 tm1dh register C 10-bit ptm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm0al register C 16-bit ptm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0 ccra low byte register bit 7~bit 0 tm0 16-bit ccra bit 7~bit 0 tm1al register C 10-bit ptm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 rev. 1.10 ?4 ?a? 1?? ?01? rev. 1.10 ? 5 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm0ah register C 16-bit ptm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0 ccra high byte register bit 7~bit 0 tm0 16-bit ccra bit 15~bit 8 tm1ah register C 10-bit ptm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 tm0rpl register C 16-bit ptm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0 ccrp low byte register bit 7~bit 0 tm0 16-bit ccrp bit 7~bit 0 tm1rpl register C 10-bit ptm bit 7 6 5 4 3 2 1 0 name d ? d6 d5 d4 d ? d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1 ccrp low byte register bit 7~bit 0 tm1 10-bit ccrp bit 7~bit 0 tm0rph register C 16-bit ptm bit 7 6 5 4 3 2 1 0 name d15 d14 d1 ? d1 ? d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0 ccrp high byte register bit 7~bit 0 tm0 16-bit ccrp bit 15~bit 8 rev. 1.10 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.10 ?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tm1rph register C 10-bit ptm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1 ccrp high byte register bit 1~bit 0 tm1 10-bit ccrp bit 9~bit 8 periodic type tm operation modes the periodic t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. rev. 1.10 ?6 ?a? 1?? ?01? rev. 1.10 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value 0xffff or 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared b? ccrp value pause resume stop counter restart tncclr = 0; tn? [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected b? tnaf flag. remains high until reset b? tnon bit output pin reset to initial value output controlled b? other pin-shared function output inverts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0 C a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge rev. 1.10 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.10 ?9 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value 0xffff or 0x?ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared b? ccra value pause resume stop counter restart tncclr = 1; tn? [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected b? tnaf flag. remains high until reset b? tnon bit output pin reset to initial value output controlled b? other pin-shared function output inverts when tnpol is high t1pf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode C tncclr=1 note: 1. w ith tncclr=1 C a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1 rev. 1.10 ?8 ?a? 1?? ?01? rev. 1.10 ? 9 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control, etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t ncclr bi t ha s no e ffect a s t he pw m period. both of the ccrp and ccra registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycl e. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit ptm, pwm mode period duty ccrp=0 ccrp=1~655 ? 5 ccra 655 ? 5 1~655 ? 5 if f sys =16mhz, tm clock source select f sys /4, ccrp=512 and ccra=128, the ptm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%, if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 10-bit ptm, pwm mode period duty ccrp=0 ccrp=1~10 ?? ccra 10 ? 4 1~10 ?? if f sys =16mhz, tm clock source select f sys /4, ccrp=512 and ccra=128, the ptm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/512=25%, if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. rev. 1.10 80 ? a ? 1 ?? ? 01 ? rev. 1.10 81 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter cleared b? ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tn? [1:0] = 10 pw? dut? c?cle set b? ccra pw? resumes operation output controlled b? other pin-shared function output inverts when tnpol = 1 pw? period set b? ccrp t? o/p pin (tnoc=0) pwm mode note: 1. here counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.10 80 ?a? 1?? ?01? rev. 1.10 81 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu single pulse output mode to se lect t his mode , bit s t nm1 and t nm0 i n t he t mnc1 regi ster should be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr is not used in this mode. ? ? ? ? ? ? ? ? ? ? ? single pulse generation rev. 1.10 8 ? ? a ? 1 ?? ? 01 ? rev. 1.10 8? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf t? o/p pin (tnoc=1) time counter stopped b? ccra pause resume counter stops b? software counter reset when tnon returns high tn? [1:0] = 10 ; tnio [1:0] = 11 pulse width set b? ccra output inverts when tnpol = 1 no ccrp interrupts generated t? o/p pin (tnoc=0) tckn pin software trigger cleared b? ccra match tckn pin trigger auto. set b? tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed rev. 1.10 8? ?a? 1?? ?01? rev. 1.10 8 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn_0, tpn_1 or tckn pin, selected by the tncapts bit in the tm1c0 register . the input pin active edge can be eit her a rising edge, a falling edge or both rising and falling edges; the act ive edge transi tion type is sel ected using the tnio1 and tnio0 bit s in t he tmnc1 regist er. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0, tpn_1 or tckn pin the present value in the c ounter wi ll be l atched i nto t he ccra re gisters a nd a t m i nterrupt ge nerated. irrespec tive of what events occur on the tpn_0, tpn_1 or tckn pin the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse wi dths. the tnio1 and tnio0 bit s ca n se lect the ac tive tri gger edge on the tpn_0, tpn_1 or tckn pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0, tpn_1 or tckn pin, however it must be noted that the counter will continue to run. as the tpn_0, tpn_1 or tckn pin is pin shared with other functions, care must be taken if the tm1 is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnoc and tnpol bits are not used in this mode. rev. 1.10 84 ? a ? 1 ?? ? 01 ? rev. 1.10 85 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared b? ccrp pause resume counter reset tn? [1:0] = 01 t? capture pin tpn_x or tckn xx counter stop tnio [1:0] value xx yy xx yy active edge active edge active edge 00 C rising edge 01 C falling edge 10 C both edges 11 C disable capture capture input mode note: 1. tnm [1:0]=01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero rev. 1.10 84 ?a? 1?? ?01? rev. 1.10 85 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. input channels channel select bits external input pins 4 acs4 ? acs 1~acs0 an0~an ? the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers. ? ?? ? ? ? ? ? ? ? ? - ? ? ? ?? ? ? ? ? ? ??? ? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d ? d ? d1 d0 adrl(adrfs=1) d ? d6 d5 d4 d ? d ? d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d ? d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs1 acs0 adcr1 acs4 vbgen vrefs adck ? adck1 adck0 acerl ace ? ace ? ace1 ace0 a/d converter register list rev. 1.10 86 ? a ? 1 ?? ? 01 ? rev. 1.10 8? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow byt e re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d ? d6 d5 d4 d ? d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d ? d6 d5 d4 d ? d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 a nd acerl a re provide d. t hese 8-bi t re gisters de fne func tions such a s t he sel ection of which analog channel is connected to the internal a/d converter , the digitised data format, the a/d cloc k source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs1~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register define the adc input channel number . as the device contains only one actual analog to digital converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter . it is the function of the acs1~acs0 and acs4 bits to determine which analog channel input pins or internal v bg is actually connected to the internal a/d converter. the acerl control register contains the ace3~a ce0 bits which determine which pins on pa0~pa3 are used as analog inputs for the a/d converter input and which pins are not to be used as the a /d converter input. s etting the corres ponding bit high w ill s elect the a /d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be re moved. in a ddition, a ny i nternal pu ll-high re sistors c onnected t o t hese pi ns wi ll be automatically removed if the pin is selected to be an a/d input. rev. 1.10 86 ?a? 1?? ?01? rev. 1.10 8 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs1 acs0 r/w r/w r r/w r/w r/w r/w por 0 1 1 0 0 0 b it 7 start : start the a/d conversion 0 1 0: start 0 1: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. b it 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. b it 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. b it 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~2 unimplemented, read as 0 b it 1~0 acs1~acs0 : select a/d channel (when acs4 is 0) 00: an0 01: an1 10: an2 11: an3 these are the a/d channel select control bits. as there is only one internal hardware a/d converter , each of the four a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high, then the internal v bg will be routed to the a/d converter. rev. 1.10 88 ? a ? 1 ?? ? 01 ? rev. 1.10 89 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 vbgen vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 b it 7 acs4 : selecte internal v bg as adc input control 0: disable 1: enable this bi t e nables v bg t o be c onnected t o t he a/ d c onverter. t he vbge n bi t m ust frst have been set to enable the bandgap circuit v bg voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap v bg voltage will be routed to the a/d converter and the other a/d input channels disconnected. b it 6 vbgen : internal v bg control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap v bg voltage can be used by the a/d converter . if v bg is not used by the a/d converter and the l vr/lvd function is disabled then the bandgap reference circuit will be automatically switched of f to conserve power . when v bg is switched on for use by the a/d converter , a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. b it 5 unimplemented, read as "0" b it 4 vrefs : selecte adc reference voltage 0: internal adc power 1: v ref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high then the a/d converter reference voltage is supplied on the external v ref pin. if the pin is low then the internal reference is used which is taken from the power supply pin vdd. b it 3 unimplemented, read as "0" b it 2~0 adck2~adck0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. rev. 1.10 88 ?a? 1?? ?01? rev. 1.10 89 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu acerl register bit 7 6 5 4 3 2 1 0 name ace ? ace ? ace1 ace0 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as 0 b it 3 ace3 : defne pa 3 is a/d input or not 0: not a/d input 1: a/d input, an3 b it 2 ace2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 b it 1 ace1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 b it 0 ace0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit i n t he adcr0 regi ster i s use d t o i ndicate whe n t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b. doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. rev. 1.10 90 ? a ? 1 ?? ? 01 ? rev. 1.10 91 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1 ? hz 1s ? s 4s 8s 16s* ?? s* 64s* undefned ?? hz 500ns 1s ? s 4s 8s 16s* ?? s* undefned 4 ? hz ? 50ns* 500ns 1s ? s 4s 8s 16s* undefned 8 ? hz 1 ? 5ns* ? 50ns* 500ns 1s ? s 4s 8s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace3~ace0 bits in the acerl register , if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically . a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on p a3~pa0 as well as other functions. the ace3~ace0 bits in the acerl register determines whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace3~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup t hrough register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the ace3~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin vref however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref . ? ? ? ?? ? ? ? a/d input structure rev. 1.10 90 ?a? 1?? ?01? rev. 1.10 91 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs1~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace3~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade , must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr 0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. rev. 1.10 9 ? ? a ? 1 ?? ? 01 ? rev. 1.10 9? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period. ? ?? ? ? ? ? ? ? ? - ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contain s a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )/4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (v dd or v ref )/4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level. rev. 1.10 9? ?a? 1?? ?01? rev. 1.10 9 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ? ? ? ? ? ? ?? ? ? ? ideal a/d transfer function a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st example, t he m ethod o f p olling t he e ocb b it i n t he adcr0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off v bg clr adoff mov a,0fh ; setup acerl to confgure pins an0~an3 mov ac erl,a mov a,0 1 h mov a dcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr s tart ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : : jmp s tart_conversion ; start next a/d conversion rev. 1.10 94 ? a ? 1 ?? ? 01 ? rev. 1.10 95 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off v bg clr adoff mov a,0fh ; setup acerl to confgure pins an0~an3 mov ac erl,a mov a,0 1 h mov a dcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr s tart ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set e mi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov s tatus_stack,a ; save status to user defned memory : : mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti rev. 1.10 94 ?a? 1?? ?01? rev. 1.10 95 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu complementary pwm output the device provides a complementary output pair of signals which can be used as a pwm driver signal. the signal is sourced from the tm1 output signal, tp1. for pmos type upper side driving, the pwm output is an active low signal while for nmos type lower side driving the pwm output is an active high signal. when these complementary pwm outputs are both used to drive the upper and low sides, the dead time generator will automatically be enabled and a dead time, which is programmable us ing the d tpsc and d t bits in the cp r register , w ill be inserted to prevent excessive d c currents . the dead time w ill be inserted whenever the rising edge of the dead time generator i nput si gnal o ccurs. w ith a d ead t ime i nsertion, t he o utput si gnals a re e ventually se nt out to the external power transistors. the dead time generator will only be enabled if both of the complementary outputs are used, as determined by the outcp bits in the tmpc register. tp1 dead time generator dtpsc [1:0] prescaler f h a b dt [2:0] e c d pwmh (driving upper side pmos, active low) pwml (driving lower side nmos, active high) f d complementary pwm output block diagram tp1 a b c d e dead time dead time dead time dead time dead time dead time complementary pwm output waveform rev. 1.10 96 ? a ? 1 ?? ? 01 ? rev. 1.10 9? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu cpr register bit 7 6 5 4 3 2 1 0 name dtpsc1 dtpsc0 dt ? dt1 dt0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 b it 7~5 unimplemented, read as "0" b it 4 ~3 dtpsc1~dtpsc0 : dead time prescaler division ratio select 00: f d =f h /1 01: f d =f h /2 10: f d =f h /4 11: f d =f h /8 b it 2~0 dt2~dt0 : dead time select, t d =1/f d 000: dead time is [(1/f d )-(1/f h )]~(1/f d ) 001: dead time is [(2/f d )-(1/f h )]~(2/f d ) 010: dead time is [(3/f d )-(1/f h )]~(3/f d ) 011: dead time is [(4/f d )-(1/f h )]~(4/f d ) 100: dead time is [(5/f d )-(1/f h )]~(5/f d ) 101: dead time is [(6/f d )-(1/f h )]~(6/f d ) 110: dead time is [(7/f d )-(1/f h )]~(7/f d ) 111: dead time is [(8/f d )-(1/f h )]~(8/f d ) over voltage protection the device incl udes an over voltage protection function which provi des a protection mechanism for the applications . t o prevent the output voltage from exceeding s pecifc voltage level, the o vp input v oltage i s c ompared wi th a r eference v oltage g enerated b y a 6 -bit d/ a c onverter. t he 6 -bit d/a converter power is supplied by the external power pin named dapwr. once the ovp input voltage is greater than the reference voltage, it will force the outh and outl signals inactive, i.e., the outh signal will be forced into a high state and the outl signal will be forced into a low state before the polarity control, to turn the external mos off for over voltage protection. the outh and outl signals can be forced to an inactive state when an over voltage event occurs. if an over voltage event occurs, the corresponding interrupt will be generated. once the over voltage condition has disappeared, the outh and outl signals will recover to drive the pwm output. more information for the outh and outl signal output control is described in the tmpc register. ca to adc dapwr 6 bit d/a ovp (interrupt & flag) ovp1en pwmh ovp0en ovpr[5:0] ovp outhn m u x 0 tp1 outcp1 outcp0 1 m u x 0 1 pwml tp1 outh outln outl over voltage protection block diagram rev. 1.10 96 ?a? 1?? ?01? rev. 1.10 9 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ovp register overall operation of the over voltage protection is controlled using several registers . one register is used to provide the reference voltages for the over voltage protection together with the d/a converter enable control bit. there is one register used to cancel out the comparator input of fset. the remaining two registers are control registers which control the ovp function, pin function, complementary pw m out put pa ir pol arity a nd c omparator de bounce t ime t ogether wi th t he hysteresis function. for a more detailed description regarding the input of fset voltage cancellation procedures, refer to the corresponding application notes on the holtek website. register name bit 7 6 5 4 3 2 1 0 ovpref dapc ovpr5 ovpr4 ovpr ? ovpr ? ovpr1 ovpr0 ocvpr0 ovpen ovp1en ovp0en chyaen ocvpr1 ovpc outhn outln cax dba1 dba0 ocvpr ? caof ? cars caof5 caof4 caof ? caof ? caof1 caof0 ovp register lists ovpref register bit 7 6 5 4 3 2 1 0 name dapc ovpr5 ovpr4 ovpr ? ovpr ? ovpr1 ovpr0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 dapc: d/a converter power source selection 0: from the vdd pin 1: from the dapwr pin b it 6 unimplemented, read as "0" b it 5~0 ovpr5~ovpr0 : over voltage protection reference voltage select ovp reference voltage =(dapwr/64)ovpr [5:0], where ovpr [5:0] is in decimal notation . rev. 1.10 98 ? a ? 1 ?? ? 01 ? rev. 1.10 99 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ocvpr0 register bit 7 6 5 4 3 2 1 0 name ovpen ovp1en ovp0en chy aen r/w r/w r/w r/w r/w por 0 0 0 0 b it 7 unimplemented, read as "0" bit 6 ovpen : over v oltage protection function enable control 0: disable 1: enable if the ovpen bit is cleared to 0, the over voltage protection function is disabled and no power will be consumed . this results in the comparator and d/a converter all being switched off. bit 5~4 unimplemented, read as "0" bit 3 ovp1en : outl over v oltage protection enable control 0: disable 1: enable this b it i s u sed t o c ontrol wh ether t he out l si gnal i s f orced i nto a n i nactive st ate when an over voltage condition occurs. if the ovpen and ovp1en bits both are set to 1, the outl signal will be forced inactive when an over voltage condition occurs. if the outl signal protection function is disabled by clearing the ovp1en bit to 0, the outl signal will not be affected when an over voltage condition occurs. bit 2 ovp0en : outh over v oltage protection enable control 0: disable 1: enable this bi t i s use d t o c ontrol whe ther t he outh si gnal i s force d i nto a n i nactive st ate when an over voltage condition occurs. if the ovpen and ovp0en bits both are set to 1, the outh signal will be forced inactive when an over voltage condition occurs. if the outh signal protection function is disabled by clearing the ovp0en bit to 0, the outh signal will not be affected when an over voltage condition occurs. bit 1 unimplemented, read as 0. bit 0 chyaen : over v oltage protection comparator hysteresis enable control 0: disable 1: enable rev. 1.10 98 ?a? 1?? ?01? rev. 1.10 99 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ocvpr1 register bit 7 6 5 4 3 2 1 0 name ovpc outhn outln cax dba1 dba0 r/w r/w r/w r/w r r/w r/w por 0 1 1 x 0 0 x: unknown bi t 7 unimplemented, read as 0 bit 6 ovpc : over v oltage protection pin control 0: ovp pin is disabled 1: ovp pin is enabled bit 5 outhn: outh signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the outh signal is inverted or not before output. bit 4 outln: outl signal inverting control 0: non-inverted 1: inverted this bit is used to control whether the outl signal is inverted or not before output. bit 3 cax: over v oltage protection comparator digital output 0: positive input voltage < negative input voltage 1: positive input voltage > negative input voltage bit 2 unimplemented, read as 0. bit 1~0 dba1~dba0 : over v oltage protection comparator debounce t ime select 00: no debounce 01: debounce time=(3~4) 1/f h 10: debounce time=(7~8) 1/f h 11: debounce time=(15~16) 1/f h rev. 1.10 100 ? a ? 1 ?? ? 01 ? rev. 1.10 101 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ocvpr2 register bit 7 6 5 4 3 2 1 0 name caof ? cars caof5 caof4 caof ? caof ? caof1 caof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit 7 caofm : over v oltage protection comparator input offset v oltage cancellation mode select 0: comparator mode 1: input offset v oltage cancellation mode bit 6 cars : over v oltage protection comparator offset v oltage cancellation reference input select 0: comparator negative input selected 1: comparator positive input selected bit 5~0 caof5~caof0 : over v oltage protection comparator input v oltage offset cancellation setting comparator cancellation function calibrate its input offset voltage before using the comparator. the calibration steps are as following: ? set caomf=1 to setup the offset cancellation mode, here s3 is closed. ? set cars to select which input pin is to be used as the reference voltage C s1 or s2 is closed. ? adjust caof [4:0] until the output status changes. ? set caomf = 0 to enter the normal comparator mode. rev. 1.10 100 ?a? 1?? ?01? rev. 1.10 101 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions . the external interrupts are generated by the action of the external int0 and int1 pins, while the internal interrupts are generated by various internal functions such as the tms, t ime base, lvd, over v oltage protection and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the registers fall into three categories. the frst is the intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi4 registers which setup the multi- function i nterrupts. fi nally t here i s a n i nteg r egister t o se tup t he e xternal i nterrupt t rigger e dge type. each register contains a number of enable bits to enable or disable individual interrupts as well as i nterrupt fa gs t o i ndicate t he p resence o f a n i nterrupt r equest. t he n aming c onvention o f t hese follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global e ? i intn pins intne intnf n=0~1 over voltage protection interrupt ovpe ovpf ? ulti-function ? fne ? fnf n=0~4 a/d converter ade adf time base tbne tbnf n=0~1 lvd lve lvf t ? tnpe tnpf n=0~ ? tnae tnaf interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 ? f0f ovpf int0f ? f0e ovpe int0e e ? i intc1 ? f4f ? f ? f ? f ? f ? f1f ? f4e ? f ? e ? f ? e ? f1e intc ? int1f tb1f tb0f adf int1e tb1e tb0e ade ? fi0 t0af t0pf t0ae t0pe ? fi1 t1af t1pf t1ae t1pe ? fi ? t ? af t ? pf t ? ae t ? pe ? fi ? t ? af t ? pf t ? ae t ? pe ? fi4 lvf lve interrupt register list rev. 1.10 10 ? ? a ? 1 ?? ? 01 ? rev. 1.10 10? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 b it 7~4 unimplemented, read as "0" b it 3~2 int1s1, int1s0 : defnes int1 interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt b it 1~0 int0s1, int0s0 : defnes int0 interrupt active edge 00 : disabled interrupt 0 1: rising edge interrupt 10 : falling edge interrupt 11 : dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 name ? f0f ovpf int0f ? f0e ovpe int0e e ? i r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f: multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 5 ovpf: over v oltage protection interrupt request fag 0: no request 1: interrupt request bit 4 int0f: int0 pin interrupt request fag 0: no request 1: interrupt request bit 3 mf0e: multi-function 0 interrupt control 0: disable 1: enable bit 2 ovpe: over v oltage protection interrupt control 0: disable 1: enable bit 1 int0e: int0 pin interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable rev. 1.10 10? ?a? 1?? ?01? rev. 1.10 10 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu intc1 register bit 7 6 5 4 3 2 1 0 name ? f4f ? f ? f ? f ? f ? f1f ? f4e ? f ? e ? f ? e ? f1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf4f: multi-function 4 interrupt request fag 0: no request 1: interrupt request bit 6 mf3f: multi-function 3 interrupt request fag 0: no request 1: interrupt request bit 5 mf2f: multi-function 2 interrupt request fag 0: no request 1: interrupt request bit 4 mf1f: multi-function 1 interrupt request fag 0: no request 1: interrupt request bit 3 mf4e: multi-function 4 interrupt control 0: disable 1: enable bit 2 mf3e: multi-function 3 interrupt control 0: disable 1: enable bit 1 mf2e: multi-function 2 interrupt control 0: disable 1: enable bit 0 mf1e: multi-function 1 interrupt control 0: disable 1: enable rev. 1.10 104 ? a ? 1 ?? ? 01 ? rev. 1.10 105 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu intc2 register bit 7 6 5 4 3 2 1 0 name int1f tb1f tb0f adf int1e tb1e tb0e ade r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int1f: int1 pin interrupt request fag 0: no request 1: interrupt request bit 6 tb1f: t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 5 tb0f: t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 4 adf: a/d converter interrupt request fag 0: no request 1: interrupt request bit 3 int1e: int1 pin interrupt control 0: disable 1: enable bit 2 tb1e: t ime base 1 interrupt control 0: disable 1: enable bit 1 tb0e: t ime base 0 interrupt control 0: disable 1: enable bit 0 ade: a/d converter interrupt control 0: disable 1: enable mfi0 register bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable rev. 1.10 104 ?a? 1?? ?01? rev. 1.10 105 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu mfi1 register bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register bit 7 6 5 4 3 2 1 0 name t ? af t ? pf t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t2af: tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf: tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t2ae: tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe: tm2 comparator p match interrupt control 0: disable 1: enable rev. 1.10 106 ? a ? 1 ?? ? 01 ? rev. 1.10 10? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu mfi3 register bit 7 6 5 4 3 2 1 0 name t ? af t ? pf t ? ae t ? pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t3af: tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t3pf: tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t3ae: tm3 comparator a match interrupt control 0: disable 1: enable bit 0 t3pe: tm3 comparator p match interrupt control 0: disable 1: enable mfi4 register bit 7 6 5 4 3 2 1 0 name lvf lve r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as 0 bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3~1 unimplemented, read as 0 bit 0 lve: lvd interrupt control 0: disable 1: enable rev. 1.10 106 ?a? 1?? ?01? rev. 1.10 10 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. all o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. rev. 1.10 108 ? a ? 1 ?? ? 01 ? rev. 1.10 109 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu int0 pin int1 pin int0f int1f int0e int1e emi 04h emi 08h m. funct. 0 mf0f mf0e emi 0ch emi 10h emi 14h time base 0 tb0f tb0e emi 18h lvd lvf lve emi 1ch interrupt name request flags enable bits master enable vector emi auto disabled in isr priority high low tm1 p t1pf t1pe tm1 a t1af t1ae m. funct. 1 mf1f mf1e tm0 p t0pf t0pe tm0 a t0af t0ae interrupts contained within multi-function interrupts xxe enable bits xxf request flag, auto reset in isr legend xxf request flag, no auto reset in isr emi 20h a/d adf ade emi 24h m. funct. 2 mf2f mf2e time base 1 tb1f tb1e emi 28h emi 2ch ovp int ovpf ovpe m. funct. 3 mf3f mf3e m. funct. 4 mf4f mf4e tm2 p t2pf t2pe tm2 a t2af t2ae tm3 p t3pf t3pe tm3 a t3af t3ae interrupt structure rev. 1.10 108 ?a? 1?? ?01? rev. 1.10 109 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu external interrupt the external interrupts are controlled by s ignal transitions on the pins in t0, in t1. a n external interrupt reques t w ill take place w hen the external interrupt reques t fags, in t0f, in t1f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e, int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f , int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ re gister i s use d t o se lect t he t ype of a ctive e dge t hat wi ll t rigger t he e xternal i nterrupt. a choice of ei ther risi ng or fall ing or both edge types ca n be chosen to tri gger an ext ernal int errupt. note that the integ register can also be used to disable the external interrupt function. ovp interrupt an ovp interrupt request will take place when the over v oltage protection interrupt request fag, ovpf, is set, which occurs when the over v oltage protection function detects an over voltage condition. t o allow the program to branch to its res pective interrupt vector addres s, the global interrupt enable bit, emi, and over v oltage protection interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an over voltage condition occurs, a subroutine call to the ovp interrupt vector , will take place. when the over v oltage protection interrupt is serviced, the emi bit wi ll be a utomatically cl eared t o disabl e othe r i nterrupts a nd the i nterrupt reque st fa g will be also automatically cleared. multi-function interrupt within the device there are up to five multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts and lvd interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags mfnf are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. t o allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-func tion request fag will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupt s and l vd interrupt, will not be automatically reset and must be manually reset by the application program. rev. 1.10 110 ? a ? 1 ?? ? 01 ? rev. 1.10 111 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 b it 7 tbon : tb0 and tb1 control bit 0: disable 1: enable b it 6 tbck : select f tb clock 0: f tbc 1: f sys /4 b it 5~4 tb11~tb10 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb b it 3 unimplemented, read as "0" b it 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb rev. 1.10 110 ?a? 1?? ?01? rev. 1.10 111 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu time base interrupt lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin the mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low voltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit , mf4e, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the l vd interrupt vector , will take place. when the low v oltage interrupt is serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared . as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and periodic t ype tms both have two interrupts each. all of the tm interrupts are contained wi thin t he mul ti-function int errupts. for e ach t m t here a re t wo i nterrupt re quest fa gs tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, em i, the res pective tm interrupt enable bit, and relevant m ulti-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situati on occurs, a subroutine call to the relevant multi-function interrupt vector locati ons, will t ake p lace. w hen t he t m i nterrupt i s se rviced, t he e mi b it wi ll b e a utomatically c leared t o disable ot her i nterrupts, howe ver onl y t he re lated mfnf fl ag wi ll be a utomatically c leared. as the t m i nterrupt r equest f lags wi ll n ot b e a utomatically c leared, t hey h ave t o b e c leared b y t he application program. rev. 1.10 11 ? ? a ? 1 ?? ? 01 ? rev. 1.10 11 ? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the multi-function interrupt request flags, mfnf , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. rev. 1.10 11 ? ?a? 1?? ?01? rev. 1.10 11 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu low voltage detector C lvd the device has a low v oltage detector function, also known as l vd. this enable s the device to monitor the power supply voltage, v dd , and provide s a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low volta ge condition will be detemined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enabl e the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 b it 7~6 unimplemented, read as "0" b it 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect b it 4 lvden : low v oltage detector control 0: disable 1: enable b it 3 unimplemented, read as "0" b it 2~0 vlvd2~vlvd0 : select lvd v oltage 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v rev. 1.10 114 ? a ? 1 ?? ? 01 ? rev. 1.10 115 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.2v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will remain active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. rev. 1.10 114 ?a? 1?? ?01? rev. 1.10 115 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu application circuits tp0 ldo 3.0v vss ir rx vdd vdd l.lcd r.lcd ls ls ls vcc1 v12 ax bx cx a b c pb0 pb1 pb2 i/o 1k k1 1k 100k 470k vin 54ht1g 1m 200k 1m 1u 1u 12v i/o outh ovp/an0 mcu vdd 54ht1g 104 boost power supply on/off control i/o lcd on/off control pulse width measure ir receiver filter HT45FH3T ls dx d pb3 l.lcd.com r.lcd.com vbat bat temp iset vin ce cn3051/cn3052 0.3 4.7uf r iset chrger ic battery rev. 1.10 116 ? a ? 1 ?? ? 01 ? rev. 1.10 11 ? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of a 4mhz system oscillator , most instructions would be implemented within 1s and branch or call instructions would be implemented within 2s. although instructi ons which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which i nvolve m anipulation of t he progra m count er l ow re gister or pcl wil l a lso t ake one m ore cycle to implemen t. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. rev. 1.10 116 ?a? 1?? ?01? rev. 1.10 11 ? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f poi nt as in the case of the call instruct ion. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.10 118 ? a ? 1 ?? ? 01 ? rev. 1.10 119 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add ? a ? [m] add a ? x adc a ? [m] adc ? a ? [m] sub a ? x sub a ? [m] sub ? a ? [m] sbc a ? [m] sbc ? a ? [m] daa [m] add data ? emor ? to acc add acc to data ? emor ? add immediate data to acc add data ? emor ? to acc with carr ? add acc to data memor ? with carr ? subtract immediate data from the acc subtract data ? emor ? from acc subtract data ? emor ? from acc with result in data ? emor ? subtract data ? emor ? from acc with carr ? subtract data ? emor ? from acc with carr ?? result in data ? emor ? decimal adjust acc for addition with result in data ? emor ? 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov c logic operation and a ? [m] or a ? [m] xor a ? [m] and ? a ? [m] or ? a ? [m] xor ? a ? [m] and a ? x or a ? x xor a ? x cpl [m] cpla [m] logical and data ? emor ? to acc logical or data ? emor ? to acc logical xor data ? emor ? to acc logical and acc to data ? emor ? logical or acc to data ? emor ? logical xor acc to data ? emor ? logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data ? emor ? complement data ? emor ? with result in acc 1 1 1 1 note 1note 1note 1 1 1 1note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data ? emor ? with result in acc increment data ? emor ? decrement data ? emor ? with result in acc decrement data ? emor ? 1 1 note 1 1note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data ? emor ? right with result in acc rotate data ? emor ? right rotate data ? emor ? right through carr ? with result in acc rotate data ? emor ? right through carr ? rotate data ? emor ? left with result in acc rotate data ? emor ? left rotate data ? emor ? left through carr ? with result in acc rotate data ? emor ? left through carr ? 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move ? ov a ? [m] ? ov [m] ? a ? ov a ? x ? ove data ? emor ? to acc ? ove acc to data ? emor ? ? ove immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data ? emor ? set bit of data ? emor ? 1 note 1 note none none rev. 1.10 118 ?a? 1?? ?01? rev. 1.10 119 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu mnemonic description cycles flag affected branch j ? p addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a ? x reti jump unconditionall ? skip if data ? emor ? is zero skip if data ? emor ? is zero with data movement to acc skip if bit i of data ? emor ? is zero skip if bit i of data ? emor ? is not zero skip if increment data ? emor ? is zero skip if decrement data ? emor ? is zero skip if increment data ? emor ? is zero with result in acc skip if decrement data ? emor ? is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt ? 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note ? ? ? ? none none none none none none none none none none none none none table read tabrd [m] tabrdl [m] read table (current page) to tblh and data ? emor ? read table (last page) to tblh and data ? emor ? ? note ? note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt ? swap [m] swapa [m] halt no operation clear data ? emor ? set data ? emor ? clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data ? emor ? swap nibbles of data ? emor ? with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to ? pdf to ? pdf to ? pdf none none to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf fags may be affected by the execution status. the t o and pdf fags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged. rev. 1.10 1 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.10 1?1 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z rev. 1.10 1?0 ?a? 1?? ?01? rev. 1.10 1 ? 1 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z rev. 1.10 1 ?? ? a ? 1 ?? ? 01 ? rev. 1.10 1?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z rev. 1.10 1?? ?a? 1?? ?01? rev. 1.10 1 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none rev. 1.10 1 ? 4 ? a ? 1 ?? ? 01 ? rev. 1.10 1?5 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none rev. 1.10 1?4 ?a? 1?? ?01? rev. 1.10 1 ? 5 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none rev. 1.10 1 ? 6 ? a ? 1 ?? ? 01 ? rev. 1.10 1?? ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c rev. 1.10 1?6 ?a? 1?? ?01? rev. 1.10 1 ?? ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none rev. 1.10 1 ? 8 ? a ? 1 ?? ? 01 ? rev. 1.10 1?9 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu tabrd [m] read ta ble to t blh a nd d ata m emory description the p rogram c ode a ddressed b y t he t able p ointer ( tbhp a nd t blp) is m oved t o t he sp ecifed data m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z rev. 1.10 1?8 ?a? 1?? ?01? rev. 1.10 1 ? 9 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information ? pb free products ? green packages products rev. 1.10 1 ? 0 ? a ? 1 ?? ? 01 ? rev. 1.10 1?1 ?a? 1?? ?01? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu 16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.15 ? c 0.008 D 0.01 ? c 0.189 D 0.19 ? d 0.054 D 0.060 e D 0.0 ? 5 D f 0.004 D 0.010 g 0.0 ?? D 0.0 ? 8 h 0.00 ? D 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 5. ? 9 D 6. ? 0 b ? .81 D ? .99 c 0. ? 0 D 0. ? 0 c 4.80 D 5.00 d 1. ?? D 1.5 ? e D 0.64 D f 0.10 D 0. ? 5 g 0.56 D 0. ? 1 h 0.18 D 0. ? 5 0 D 8 rev. 1.10 1?0 ?a? 1?? ?01? rev. 1.10 1 ? 1 ? a ? 1 ?? ? 01 ? HT45FH3T 3d glasses 8-bit flash type mcu HT45FH3T 3d glasses 8-bit flash type mcu cop ? right ? ? 01 ? b ? holtek se ? iconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however ? holtek assumes no responsibilit ? arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warrant ? or representation that such applications will be suitable without further modification ? nor recommends the use of its products for application that ma ? present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or s ? stems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. |
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